Symposium on Experiences of Porting and Optimising Code for Xeon Phi Processors

摘要

The flop-to-watt performance potentially available from Intel's Xeon Phi co-processor makes it very attractive for computational simulation. With its full x86 instruction set, cache-coherent architecture, and support for MPI and OpenMP parallelisations, it is in theory relatively straight-forward to port applications to the platform. However, a number of factors can make it difficult to obtain good performance for many codes. These factors include the relatively high core count, the low clock speed of the cores, the in-order instruction restrictions, 512-bit wide vector units, and low memory per core.