Fault Tolerant Scheduling with Enhanced Performance for Onboard Computers: Evaluation

摘要

Dependability as a factor in safety critical systems like satellite launch vehicles avoids catastrophic effects. Onboard computers with traditional dual redundancy mechanism for fault tolerance performs acceptably on fault conditions but underutilization of computational resources are prevalent during fault-free operation. Augmentation of computational resources in such systems with a task allocation paradigm dealt with in earlier studies, helps in achieving better performance and improved safety margins keeping the constraints like size, weight, and power. Testing of a fault tolerant algorithm for a flexible augmented model for hardware fault has been implemented with simulation using TORSCHE real-time scheduling tool and a user interface using Matlab GUI. Experimental hardware implementation on ARM Cortex-M has also been developed. Using performance metrics and verification for faults tolerance, an evaluation of the system performance projects the benefits of implementing such models for weight critical space applications.