Low-power digital signal processor design for a hearing aid

摘要

A new low-power digital signal processor (DSP) design for a hearing aid system is proposed. A stochastic method was applied to the DSP in order to fulfill the needs of the hearing aid system, considered to be an error-tolerant system. The different blocks that form the DSP are presented in this paper. The implementation and layout were performed and simulated using a 90 nm CMOS process. Simulation results showed excellent energy consumption savings in the range of 4.5x to 10x of the proposed DSP design when compared to similar DSPs.