The Design and Implementation of Reconfigurable Cipher Unit on FPGA

摘要

Encryption is the core of security technology. The paper managed to design and implement a kind of reconfigurable cipher unit based on the 3DES/AES and optimized by FPGA technology, which can effectively support diverse cryptographic algorithms and can meet the demand on system performance and flexibility. The unit uses hardware description language VHDL, layout and wire on QuartusII 8.0. Finally the system is downloaded to DE2 for testing. The design hardware structure is simple, flexibility, security, which can be widely used in the field of information security.