Interleaved Switching of Parallel ZVS Hysteresis Current Controlled Inverters

摘要

A robust self-interleaving mechanism for parallel hysteresis current controlled inverters is proposed,with sustained switching under all load conditions. A fast interleaving technique that can be applied for normal load conditions is combined with a self-interleaving mechanism,which ensures correct switching during voltage clamping operation. A minimum switching frequency and maximum duty cycle is guaranteed under all load conditions enabling the use of low-cost bootstrap circuits to drive the highside switches. The interleaving approach results in reduced volume of the passive components and better dynamic response. The self-interleaving mechanism was analyzed using the state-plane method, extended to multiple parallel modules. Simulations were conducted to verify the combined operation of both methods and measurements were performed on a 3 kW prototype zero-voltage-switching inverter with a discrete hysteresis current controller.