Design of high-order type-II delay-locked loops using a Gaussian transfer function approach

摘要

In this article, a method of designing high-order DLLs is presented and verified through both simulations and physical experiments. The general approach is based on selecting the transfer function of the closed-loop DLL and deriving the loop filter behavior based on the gain of the phase-detector and voltage-controlled delay line. The proposed approach does not rely on the principle of design based on achieving a desired phase margin specifications but rather is based on selecting a closed-loop DLL behavior based on a desired Gaussian transfer function. Experimental results are provided to support the claims.