A Digital Centric Transmitter Architecture with Arbitrary Ratio Baseband-to-LO Upsampling

摘要

This paper presents a digital centric transmitter architecture with clock domain transition from the baseband clock to a clock derived from the local oscillator of the proposed transmitter. Both clock domains are asynchronous and variable in general, hence this transistion block represents the key building block of the digital signal processing chain. It consists of a synchronizing stage, a timing control unit, and a modified Generalized Farrow upsample filter which allows to implement further upsample stages using simple integer-ratio CIC filters. The architecture is well appropriate for low energy digital-centric hardware designs. Highly reconfigurable, it is applied in a state-of-the-art multimode multistandard transmitter with radio frequency DAC frontend, suitable for WLAN, UMTS, LTE and other recent standards.