Defect Tolerant Prefix Adder Design

摘要

This paper introduces a defect tolerant 64-bit Sklansky prefix adder, designed with the goal of increasing itsreliability and extending its lifetime in the presence of hard faults. We consider defect tolerance for earlytransistor wear-out by exploring the design of fine-grained reconfigurable logic. The approach involves enablingspare processing elements to replace defective elements. Power gating techniques are used to disable faulty logicblocks and enable spare logic. Minimum sized transistors are used for spare processing elements to reduce areaoverhead, and simplify reconfiguration interconnect. The performance of the design is compared to a baseline, non-repairing design using the cost metrics of: areaoverhead, power consumption, and performance in the fault free and faulty case.