A-Priori Wirelength and Interconnect Estimation Based on Circuit Characteristics

摘要

Interconnect prediction is very important for early feasibility studies in modern design flows. Most of the interconnect estimation techniques estimate average or total wirelength and some qualitative measure of routing demand for circuits. A-priori techniques estimate these characteristics without actually performing circuit placement. We propose a new a-priori interconnect and wirelength estimation methodology for island style FPGAs. For a given design, we estimate bounding box lengths of all nets for an optimized placement and the minimum number of tracks per channel required for successful routing on an FPGA device. We analyze the structural characteristics of circuits and limitations posed by the FPGA architecture to derive a consistent model for wire-length and routing demand estimation. Our results show that we have an average error of 11.6% w.r.to bounding box spans measured from the optimized layout using VPR. Also, the number of routing tracks is predicted with an average error of 6.1% of the detailed routing results from VPR.