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Experiences in developing a research-focused project course: IP-core based IC design enabled by 3D wafer bonding

机译:开发研究专注的项目课程的经验:3D晶圆键合的IP核心IC设计

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摘要

Three-dimensional (3D) integrations offer the potential of reducing fabrication and performance limitations of future generations of planar ICs. Our approach using dielectrics as the bonding glue layer provides a monolithic 3D integration process, which is fully compatible with back-end-of-the-line processing. This 3D technology enables heterogeneous systems, such as future electronic and photonic systems using a mix-and-match hard IP core design approach. We offer a new course on core-based IC design and technology, with both 2D and 3D implementations.
机译:三维(3D)集成提供了减少平面IC的未来几代制造和性能限制的潜力。我们使用电介质作为粘合胶层的方法提供了一种单片3D集成过程,其与后端型处理完全兼容。该3D技术可实现异构系统,例如使用混合和匹配的硬IP核心设计方法的未来电子和光子系统。我们提供了基于核心的IC设计和技术的新课程,具有2D和3D实现。

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