A Robust PLL Technique using a Digital Lock-In Amplifier under the Non-Sinusoidal Grid Conditions

摘要

Due to the recent increasing use of nonlinear loads and Grid Connected Inverters (GCIs), the harmonics are also increasing in the grid. The detrimental effects of the harmonics in the grid include the heating in the equipment and conductors, the misfiring in variable speed drives, the torque pulsations in motors and the asynchronization of the GCIs. Therefore, the standard such as IEEE 519 and P1547 forces the GCIs to meet a certain level of output quality in terms of harmonics, phase and frequency variation. In order to inject the pure active power to the grid, the synchronization between the grid and a GCI by a highperformance Phase Locked Loops (PLLs) is essential. Several kinds of PLL methods to synchronize the GCI under the distorted grid condition have been proposed. However, their performances are significantly degraded under the distorted grid condition, especially with a DC off-set and harmonics. In this paper a novel Digital Lock-in Amplifier (DLA) based PLL is proposed to improve the performance of the PLL under the highly distorted grid condition including the power quality events. Since the proposed DLA-PLL is composed of a robust Phase Sensitive detector (PSD), it is immune to any frequency component except the fundamental and the DC off-set present in the grid can be completely rejected. The superiority of the proposed DLA-PLL is proved by the simulation and experiments by comparing it to the results obtained with the six kinds of conventional PLL methods widely used under distorted grid condition.