Many fields of science, engineering, finance, mathematical optimization methods, Artificial Neural Networks, signal and image processing algorithms requires the operations and manipulations of real numbers. Floating-point operations are most extensively adopted approach for exploiting real numbers. The speed of Floating-point arithmetic unit is very crucial performance parameter which impinges the operation of the system. On that account a 32 bit floating point arithmetic unit is designed for different applications which insists for eminent speed. The intent of this design is to reduce the area and combinational path delay to enhance the speed of operation which is attained by parallelism in multiplier which is used for mantissa multiplication. For Floating-point multiplier Booth recoded multiplier is used where the number of partial product are reduced which in turns boost the speed of multiplication. The proposed module is implemented on Spartan 6 FPGA. Performance of the floating point arithmetic unit is compared with latest research papers regarding delay and it is ascertained that there is 59% of optimization in critical path delay of floating point multiplier and 50 % of optimization of floating point adder. The result illustrates that proposed arithmetic unit has a great impact on convalescent the speed and area of the design.
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