Software Logical Structure Verification Method by Modeling Implemented Specification

摘要

In component testing for a single function, a functional black box testing based on specification of the function and a white box testing based on the program structure are performed. However, It is difficult to verify a logical correctness of the program by these testing methods. In this paper, a novel verification method to achieve it is proposed. Conventional testing usually compares output from program with expected output, our method models the function specification and the implemented specification as a Decision Table format, then compare them. We applied this method to some commercial programs. As a result, we could verify correctness of the logics implemented in the programs.