Combining Simulation and Formal Verification for Integrated Circuit Design Validation

摘要

The correct design of complex hardware continues to challenge engineers. Bugs in a design that are not uncovered in early design stage can be extremely expensive. Simulation is a predominantly used tool to validate a design in industry. Formal verification overcomes the weakness of exhaustive simulation by applying mathematical methodologies to validate a design. The work described here focuses upon a combinational technique that integrates the best characteristics of both simulation and formal verification methods to provide an effective design validation tool, referred as IDV. The novelty in this approach consists of three components, a circuit complexity analyzer, a partitioning tool and a coverage analysis unit. The circuit complexity analyzer and partitioning tool partition a large design and feed sub-components to different verification and/or simulation tools based upon known existing strengths of modem verification and simulation tools. The coverage analysis unit computes the coverage rate of design validation and improves the coverage by further partitioning. Various tools comprising IDV are evaluated and an example is used to illustrate the overall validation process. The overall process successfully validates the example to a high coverage rate within a short time. The experimental result shows that our approach is a very promising design validation method.