This paper presents an end-to-end analysis of how an architecture that enables efficient communication can be realized on an advanced hardware computing platform. It describes everything from the high-level software constructs needed to handle efficient buffering and synchronization on the host PC, to the design of the hardware modules needed for platform communication. The communication paths are followed completely: from disk, to memory, to the acceleration platform, and back again. The system is over 99% efficient, enabling the storage of as many results as possible without sacrificing speed in the computational core.
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