ADVANCED PROCESS MODULES FOR SCALED ULSIs

摘要

Ultra-small MOSFET device design, High-k gate-stacked devices and Low-k/Cu interconnects are described from the viewpoint of process modules of scaled ULSIs. Sub-lOnm planar bulk-CMOS devices were demonstrated by the strict impurity profile control in source/drain (S/D) junction and channel region. Good switching characteristics were observed for n-/p-MOSFETs with 5nm gate length. For High-k gate-stacked MOSFETs, poly-Si gated MOSFETs with HfSiO(1.8nm) insulator were demonstrated. A symmetrical set of Vth's for NFET and PFET was realized for low power device operation. Poly-Si/HfSiO gate-stacked CMOS devices have shown low loff(N/PFET: 4.8/3.6pA/um) and high lon(N/PFET: 469/140 u.A/Lim). For advanced Low-k interconnect technology, a highly reliable Low-k/Cu interconnect were shown with 180nm/200nm-pitched lines connected through iplOOnm-vias. A porous SiOCH film (k=2.5) with sub-nanometer pores is introduced for the inter-metal dielectrics (IMD).