A TDMA/TDD Processing Unit IP Core for WLL Cell Station Targeting FPGA Implementation

摘要

This paper describes how the TDMA/TDD processing unit, which is conventionally implemented as an ASIC, can be successfully adopted using FPGA technology. The TDMA/TDD soft IP. with its internal memory requirement, is particularly suitable for FPGA implementation. The design was successfully tested at the laboratory stage as a component for a cell station of a PHS wireless system to be used in Wireless Local Loop systems as a viable alternative for rural telephone systems. The core, when implemented on a cost-effective FPGA. is able to operate at up to 30MHz.