COPPER DEPOSITION AND SUBSEQUENT GRAIN STRUCTURE EVOLUTION IN NARROW LINES

摘要

Electroplated copper has become the method of choice for filling narrow interconnect features in the back-end-of-line processing for microelectronics applications. Through the use of additives a void free deposit can be obtained by inducing a filling from the bottom up. However, the accompanying sub-critical grain size results in a recrystallization that proceeds even at room temperature. This process is strongly dependent on plating conditions and the additives used. The resulting differences are studied through line resistivity and real-time SEM grain growth monitoring at elevated temperatures. The present understanding and our efforts to improve it are presented.