Efficient Execution of Erasure Codes on AMD APU Architecture

摘要

Erasure codes such as Reed-Solomon codes can improve the availability of distributed storage in comparison with replication systems. In previous studies we investigated implementation of these codes on multi/many-core architectures, such as Cell/B.E. and GPUs. In particular, it was shown that bandwidth of PCIe bus is a bottleneck for the implementation on GPUs. In this paper, we focus on investigation how to map systematically the Reed-Solomon erasure codes onto the AMD Accelerated Processing Unit (APU), a new heterogeneous multi/many-core architecture. This architecture combines CPU and GPU in a single chip, eliminating costly transfers between them through the PCI bus. Moreover, APU processors combine some features of Cell/B.E. processors and many-core GPUs, allowing for both vectorization and SIMT processing simultaneously. Based on the previous works, the method for the systematic mapping of computation kernels of Reed-Solomon and Cauchy Reed-Solomon algorithms onto the AMD APU architecture is proposed. This method takes into account properties of the architecture on all the levels of its parallel processing hierarchy.