Design verification and DFT for an embedded reconfigurable low-power multiplier in system-on-chip applications

摘要

A pseudo-exhaustive design verification approach is presented in this paper for an embedded low-power reconfigurable parallel multiplier in System-on-Chip (SoC) applications. The proposed approach greatly reduces the size of the required test bench. Also presented are Design for Testability (DFT) techniques that are utilized for this multiplier to achieve high fault coverage.