Compact and high-speed hardware architectures and logic optimization methods for the AES algorithm Rijndael are described. Encryption and decryption data paths are combined and all arithmetic components are reused. By introducing a new composite field, the S-Box structure is also optimized. An extremely small size of 5.4 Kgates is obtained for a 128-bit key Rijndael circuit using a 0.11-μm CMOS standard cell library. It requires only 0.052 mm{sup}2 of area to support both encryption and decryption with 311 Mbps throughput. By making effective use of the SPN parallel feature, the throughput can be boosted up to 2.6 Gbps for a high-speed implementation whose size is 21.3 Kgates.
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机译:描述了AES算法Rijndael的紧凑型和高速硬件架构和逻辑优化方法。组合加密和解密数据路径,所有算术组件都重复使用。通过引入新的复合字段,S盒结构也得到了优化。使用0.11-μmCMOS标准细胞库的128位键Rijndael电路获得极小的5.4 kgates。它仅需要0.052 mm {sup} 2区域来支持使用311 Mbps吞吐量的加密和解密。通过有效地利用SPN并联特征,可以将吞吐量提升至2.6 Gbps,高速实现,其大小为21.3 kgates。
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