Architectural Synthesis Exposing Parallelism and Increasing the Scheduling Scope for FPGA-based Digital Systems

摘要

Reconfigurable computing systems provide the capability for spatial/parallel computation and so can achieve important speed-ups on program execution. Compilers capable to exploit the full potential of available parallelism, able to consider the wire and gate-level flexibility of commercial FPGAs. the hierarchical memory levels offered and the reconfiguration facility, are still required and are an important focus of research. This paper presents significant achievements on compiling algorithms, abstractly described in software programming languages, to reconfigurable hardware coupled to one or more memories. To circumvent eventual inefficiencies, due to the sequential nature of the original description, this paper illustrates the use of an intermediate representation model that both preserves functional information (loop hierarchies) and represents functional parallelism. Combined with a global dataflow graph provided with program decision logic it seems to be an efficient intermediate model to represent parallelism at various levels, to exploit speculative execution and multiple flows of control, and to perform temporal partitioning. In order to enhance the scope of the scheduling phase, basic blocks are merged among loop boundaries. The paper shows results obtained with such approach versus a scheduling scheme based on the original control-flow sequence without merging basic blocks.