DFT advances in Motorola's MPC7400, a PowerPC microprocessor

摘要

Several advances have been made in the Design for Testability of the MPC7400, the first fourth generation PowerPC microprocessor. The memory Array Built-In Self-Test (ABIST) algorithms now support detecting write-recovery defects and morecomprehensive diagnostics. Delay defects can be tested with scan patterns with the Phased Locked Loop (PLL) providing the at-speed launch-capture events. Several methodology and modeling improvements increased LSSD stuck-at fault test coverage. Design for Manufacturability enhancements provide better tracking of initial silicon and fuse-based memory repair capabilities for improved yield and Time-to-Market.