An on-line bisted SRAM IP core

摘要

In digital systems design, strict reliability constraints usually impose very low fault latency and high degree of fault detection of permanent and transient faults. In particular, memory modules, as either devices or IP cores, appeared as one ofthe most critical parts. This paper presents an advanced on-line memory BIST architecture implemented as an IP core developed for telecommunication applications at Italtel SpA, the major Italian manufacturers of telecom systems. A fault latency reductionarchitecture, a code-based fault detection scheme, and an architecture-based fault avoidance have been composed to meet the required reliability constraints.