A new BIST TPG design, called low-transition random TPG (LT-RTPG), that is comprised of an LFSR, a k-input AND gate, and a T flip-flop, is presented. When used to generate test patterns for test-per-scan BIST, it decreases the number oftransitions that occur during scan shifting and hence decreases the heat dissipated during testing. Various properties of LT-RTPG's are studied and a methodology for their design is presented. Experimental results demonstrate that LT-RTPG's designed using the proposed methodology decrease the heat dissipated during BIST by significant amounts while attaining high fault coverage, especially for circuits with moderate to large number of scan inputs.
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