As component technology advances, the idea of supporting very wide band digital communication systems has become practical. Still, many applications require limited size, weight, and power, such as equipment on spaceborne platforms or commercial equipment to go into residences. In these cases there are two paths to pursue -move the analog-to-digital converter closer to the antenna, and develop ASICs to meet the form factor and power requirements of the application. Moving the analog-to-digital converter closer to the antenna, that is, sampling the signal directly at an intermediate frequency, is a major trend as ADC's to do the high speed sampling become available. This approach does away with video mixers and filters, and it enables a variety of digital signal processing methods such as polyphase architectures and multirate designs that have no parallel in analog systems. Implementing the required digital processing behind the ADC in ASICs can result in small form factors and low power consumption. But, there is a large amount of initial nonrecurring expense associated with ASIC design, so designing an ASIC that can support multiple applications is highly desirable. This article deals with the issue of designing a single digital ASIC to receive three wideband signal formats. The digital ASIC is targeted as part of the ground equipment for satellite communications systems, although it would be useful in other applications as well. The maximum information bandwidth is 500 MHz. The three bandwidths supported are 500 MHz, 125 MHz, and 40 MHz. We presume direct sampling of an IF signal at approximately 1600 MSPS with a single (non I/Q) ADC. We first present the receiver requirements. We then define a baseline architecture and two alternatives to meet the requirements. We conclude by estimating gates, power consumption, and form factors for the alternative approaches implemented in 0.18 micron CMOS ASIC technology.
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