A high speed base library and macro library design methdology for submicron and deep submicron ULSI

摘要

This paper presents a high speed base library and macro library design methodology for submicron and deep submicron ULSI. Using the libraries, a 0.6#mu#m CMOS high speed DSP chip is devleoped. To create the base and macro libraries, the effects of delay in interconnect wire and input slope were considered; the delay model was selected; the "variable parameter" cell and "buried" cell were used to correct a timing violation.