This paper presents a vertex ordering heuristic which speeds up the search process in the partitioning-based fitting algorithm. The fitting algorithm maps a sequential circuit onto a special application EPLD device, the CY7C361 from Cypress Semiconductor. The same approach can also be used for other EPLD and FPGA architectures. The vertex ordering heuristic decreases the search time from hours to seconds for more complex designs. The quality of results is not effected as the algorithm remains exact.
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