Nowadays various architectures are suggested for highly efficient image processing, including parallel processors of SIMD type, multiprocessor systems, pipelined processors, systolic arrays and pyramid machines. However, a maximal speed of algorithm execution can be reached only by specialized processor implemented on a custom chip. So merging of the properties of a specialized processor and a possibility of reprogramming in one approach should give a satisfactory result. The paper suggests a new approach to the developing of architecture of a high-speed parallel system for low-level image processing. The homogeneous computing structure (HCS) and homogeneous storing structure (HSS) are the basic elements of this approach. The high speed of the system is provided by structural method of organization of the computing process which is based on the hardware realization of all the nodes of the information graph and their interconnections. The size of the HCS matrix allows to use for each program instruction its own group of processor elements. The program is loaded once before starting to solve the problem, and the information streams processing is carried out without intermediate results storage. The data streams applied to the information inputs of the processor elements are processed in accordance with the program, moving from one element to another in the matrix of the HCS. The examples of execution of the image filtering algorithms on the system are presented.
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