A UPS inverter with zero output impedance

摘要

In this paper, a solution of a UPS inverter with zero output impedance is presented. Zero output impedance is achieved by compensation of forward voltage drop on the output inductor. In practical inverter realization, a PWM technique is used at 20 kHz switching frequency. Nominal output voltage is 115 V/400 Hz, with nominal output power of 1200 W. This solution of zero output impedance yields output voltage load regulation better than 0.2% from no load to full load, and can be easily implemented for a line frequency of 50/60 Hz. Moreover, any (even negative) desired inverter output impedance can be "preprogrammed" in the control circuit, enabling easy paralleling of two or more inverters for higher power: the higher the output impedance, the better current sharing will be obtained.