A TDM-based multibus packet switch

摘要

A novel packet switch architecture using two sets of time division multiplexed (TDM) buses is proposed. The horizontal buses collect packets from the input ports while the vertical buses distribute the packets to the output ports. The two sets of buses are connected by a set of switching elements which coordinate the connections between the horizontal buses and the vertical buses so that each vertical bus is connected to only one horizontal bus at a time. The switch has the advantages of: (1) it adds input and output ports without increasing the bus and I/O adaptor speed; (2) it is internally unbuffered; (3) it has a very simple control circuit; and (4) it has 100% potential throughput under uniform traffic. A combined analytical-simulation method is used to obtain the packet delay and packet loss probability. Numerical results show that for satisfactory performance the buses need to run about 30% faster than the input line rate. With this speedup, even at a utilization factor of 0.9, the input queue can give a packet loss of 10/sup -6/ with only 31 buffers per input adaptor. The output queue behaves essentially as an M/D/1 queue.