A new logic design timing verification technique named coded time-symbolic simulation (CTSS) is presented. Novel techniques of analyzing the results of CTSS are proposed. Simulation of logic circuits consisting of gates whose delay is specified only by its minimum and maximum values is considered. The cases of possible delay values of each gate are encoded by binary values, and all the possible combinations of the delay values are simulated by means of symbolic simulation. This simulation technique can deal with logic circuits containing feedback loops as well as combinational circuits. An efficient simulator was implemented by using a shared binary decision diagram (SBDD) as an internal representation of Boolean functions.
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机译：提出了一种新的逻辑设计时序验证技术，名为Coded Time-Symem Signal Simulation（CTS）。提出了分析CTS的结果的新颖技术。考虑由延迟仅指定其延迟和最大值的栅极组成的逻辑电路仿真。每个门的可能延迟值的情况由二进制值编码，并且通过符号模拟模拟延迟值的所有可能组合。该仿真技术可以处理包含反馈回路以及组合电路的逻辑电路。通过使用共享二进制决策图（SBDD）作为布尔函数的内部表示来实现一个有效的模拟器。
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