An approach is being implemented that utilizes sophisticated computer-aided engineering (CAE) technology to facilitate meeting US Department of Defense advanced-technology-evaluation requirements for the Very High Speed Integrated Circuits (VHSIC) program. As a first step in this direction, a VHSIC Demonstration Radar Signal Processor (VDRSP) was designed, simulated, built, and tested. The VDRSP executes a standard moving-target-indication (MTI) function at a 5-MHz complex data rate. In order to minimize cost, schedule, and glue logic requirements, the VHSIC I IBM CMAC (Complex Multiply and Accumulate Chip) was selected for this project. The final system executes at a throughput of 450 million operations per second.
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机译：正在实施一种采用复杂的计算机辅助工程（CAE）技术的方法，便于满足美国国防部门的高速集成电路（VHSIC）计划的高级技术评估要求。作为沿此方向的第一步，设计，模拟，构建和测试了VHSIC演示雷达信号处理器（VDRSP）。 VDRSP以5 MHz复杂数据速率执行标准移动目标指示（MTI）函数。为了最大限度地减少成本，时间表和胶水逻辑要求，为此项目选择了VHSIC I IBM CMAC（复杂的乘法和累积芯片）。最终系统每秒执行4.5亿运营的吞吐量。
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