Techniques for the design of VLSI architectures for direct digital frequency synthesis have been introduced that allow for the optimization of the spurious response in the presence of finite-wordlength effects. These optimization techniques exploit certain number-theoretic properties of the phase accumulator to make the exhaustive simulation of direct digital frequency synthesizer (DDFS) performance in the presence of different system nonlinearities computationally feasible. These techniques have been applied to design a 14-bit-output DDFS with a simulated spurious performance of -90.3 dB and a level of pipelining that allows a 100-MHz clock rate in a 1.25- mu m CMOS process.
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机译：已经引入了用于直接数字频率合成的VLSI架构设计的技术，其允许在有限字母长度效应存在下优化虚假响应。这些优化技术利用相位累加器的某些数字 - 理论属性，以使不同系统非线性在计算可行的情况下的直接数字频率合成器（DDFS）性能的详尽模拟。已经应用这些技术来设计具有-90.3dB的模拟杂散性能的14位输出DDF，以及允许1.25-MU M CMOS工艺中100MHz时钟速率的流水线。
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