An Efficiency Partially Compatible Test Decompression Technology Oriented RL-HC

摘要

For most intellectual property core in System-on-a-chip, larger test set is required to achieve higher fault coverage, which leads to excessive test data volume and high-test power consumption during VLSI testing. Hence, partially compatible test decompression technology oriented RL-HC is proposed to effectively alleviate this thorny problem. The unspecified bit in test data is filled according to the evaluation of Weighted Transition Metric, and then the filled test data are divided into blocks by the smallest entropy value. The determined test vectors are encoded using Run length-based Huffman Code scheme, the more frequent the blocks, the shorter the codewords, which aims at reducing the storage resource occupied by test data in system-on-a-chip. Furthermore, a partially compatible XOR decompression circuit structure is designed to avoid the compatible test vectors repeatedly loaded into scan chain, which leads to less test power consumption during scan testing. Numerous experiments are performed on the representative Benchmark circuits to verify the proposed RL-HC based test decompression scheme well, it outperforms the previous code-based scheme in the overall performance including high test compression ratio, test power consumption reduction.