Adaptive Time-Stepping Universal Line and Machine Models for Real-Time and Faster-Than-Real-Time Hardware Emulation

摘要

Transmission lines and rotating machines that widely exist in power systems should be accurately modeled in real-time electromagnetic transient (EMT) simulation for obtaining precise results for hardware-in-the-loop (HIL) applications. In the conventional EMT simulator, the time-step is fixed, which may lead to inefficiencies when the time constants of the system change. The adaptive time-stepping (ATS) method can efficaciously solve this problem; however, the ATS schemes for the universal transmission line model (ULM) and universal machine (UM) model remain to be investigated. This work derives the ATS models for ULM and UM, and the proposed ULM model is more stable than the traditional model. Both ATS models are emulated on the parallel and pipelined architecture of the FPGA. The proposed subsystem-based ATS scheme and the local truncation error (LTE) based time-step control enable the large-scale systems to be simulated in real-time and “faster-than-real-time” modes. The IEEE 39-bus system with ATS models was emulated on two interconnected FPGA boards, and the emulation results compared with PSCAD/EMTDC and fixed time-stepping (FTS) hardware emulator verified the effectiveness of the proposed models and showed that the LTE of ULM and UM can be reduced by 76.5% and 62.0% respectively compared with the FTS simulation.