ONoC-SPL: Customized Network-on-Chip (NoC) architecture and prototyping for data-intensive computation applications

摘要

Network-on-Chip (NoC) has emerged as a promising paradigm to largely alleviate the limitations exhibited by the shared-bus based systems in current System-On-Chip (SoC). These problems include the lack of scalability, clock skew, lack of support for concurrent communication, and increasing power consumption. Based upon a packet/flit switching scheme, NoC allows a concurrent transmission of data providing a higher bandwidth and performance.