A Novel Design of Fast and Low Power Pull-Up and Pull-Down Voltage Level Shifter

摘要

This article presents a low power consumption and fast voltage level shifter, which can increase the input voltage level lower or comparable to a threshold voltage to nominal voltage level and high voltage level to low voltage level. The proposed level shifter is based on a pull-up network which has regulated cross-coupled structure. This helps to enhance the switching speed and reduction of dynamic power. Furthermore, split input inverter and pMOS diode used to reduce the static power consumption. For proposed level shifter simulation results have performed in a 180 nm CMOS technology using cadence virtuoso tool. While converting supply voltage from low to the high voltage level of 0.4 V and 1.8 V, respectively at applied frequency 1 MHz, power consumption and propagation delays are 139.6 nW and 19.92 ns, respectively. And during conversion high to the low supply voltage are 1.8 V and 0.4 V, 120.2 nW and 15.31 ns, respectively.