Power Delivery Network Impedance Profile and Voltage Droop Optimization

摘要

The design process of power delivery networks (PDN) in modern computer platforms is becoming more relevant and complex due to its relationship with high-frequency effects on signal integrity. When circuits start operating, the changing current flowing through the PDN produces fluctuations creating voltage noise. Unsuccessful noise control can compromise data integrity. A suitable PDN design approach is the use of decoupling capacitors to lower the impedance profile and mitigate current surges, ensuring a small variation in the power supply voltage under significant transient current loads. An optimization approach to determine the number of decoupling capacitors in a PDN is presented in this paper, aiming at decreasing the amount of decoupling capacitors without violating the PDN design specifications, looking at both the impedance profile in the frequency domain and the resulting voltage droop in the transient time-domain.