Design oriented analysis of package power distribution systemconsidering target impedance for high performance microprocessors

摘要

This paper presents an efficient design methodology to realize theoutput impedance at the high performance microprocessor core equal to orless than the target impedance to reduce the mid-frequency core noise.Based on the frequency domain analysis of the lumped model of thepackage power distribution network (PPDN), a systematic method ofestimating capacitance and associated parasitics of decouplingcapacitors used in the distributed model of the PPDN is described. Thesimulation results of the analytical method show good correlation withthe SPICE simulation results of the distributed PPDN model to reduce theoutput impedance at the core