An ADPLL-based fast start-up technique for sensor radio frequency synthesizers

摘要

This paper proposes a technique to speed up the start-up process of frequency synthesizers for wireless sensor network (WSN) applications. The proposed technique relies on an all-digital phase-locked loop (ADPLL) architecture to preserve last known settled synthesizer state over an extended power-down period and use it on next power-up. The effect of periodic variations such as a change in die temperature is digitally compensated for by utilizing a simple least mean-square (LMS) adaptation algorithm. Simulations demonstrate that with slow ambient temperature drift, the start-up time of the frequency synthesizer can be dramatically reduced.