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DLX HOTOKADA: A design and implementation of a 32-bit dual core capable DLX microprocessor with single level cache

机译:DLX HOTOKADA:具有单级缓存的具有32位双核功能的DLX微处理器的设计和实现

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Data access in main memory units can be sufficient for processors but due to demands for faster computers nowadays, implementation of multiple cores as well as the usage of a cache to increase performance, are necessary. These two solutions were implemented using a 32-bit pipelined DLX microprocessor, resulting to a dual core capable (DCC) DLX with single-level cache in a Uniform Memory Access Architecture type. This project made use of the Shared Cache System divided into an Instruction Cache and a Data Cache to solve processor structural hazards due to coincident instruction and data access.
机译:主存储器单元中的数据访问对于处理器来说足够了,但是由于当今对更快的计算机的需求,必须实现多个内核以及使用高速缓存来提高性能。这两个解决方案是使用32位流水线DLX微处理器实现的,从而产生了具有双核功能(DCC)的DLX,具有统一内存访问体系结构类型中的单级缓存。该项目利用共享高速缓存系统(分为指令高速缓存和数据高速缓存)来解决由于指令和数据访问重合而导致的处理器结构危害。

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