首页> 外文会议>Design Automation, 1995. DAC '95. 32nd Conference on >Retiming Synchronous Circuitry with Imprecise Delays
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Retiming Synchronous Circuitry with Imprecise Delays

机译:具有不精确延迟的重定时同步电路

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Often, and certainly in the early stages of a design, the knowledge about delays is imprecise. Stochastic programming is not an adequate means to account for this imprecision. Not only is a probability distribution seldom a correct translation of the designer's delay knowledge, it also leads to inefficient algorithms. In this paper possibilistic programming is proposed for handling the retiming problem where delays are modelled as (triangular) possibilistic numbers. Beside the capability of optimizing the most possible clock cycle time and generating its possibility distribution, it allows for trade-offs between reducing clock cycle time and chances for obtaining worse solutions. It is shown that the computational complexity is the same as for retiming with exact circuit delays.
机译:通常,当然在设计的早期阶段,有关延迟的知识是不准确的。随机程序设计不足以解决这种不精确性。概率分布不仅很少正确传达设计者的延迟知识,还导致算法效率低下。在本文中,提出了一种可能的程序来处理重定时问题,其中将延迟建模为(三角形)可能的数。除了优化最可能的时钟周期时间并生成其可能性分布的功能外,它还可以在减少时钟周期时间和获得更坏解决方案的机会之间进行权衡。结果表明,计算复杂度与具有精确电路延迟的重定时相同。

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