An insight into a digital sensor for ΔΣ modulatorinvestigation

摘要

Even an ideal ΔΣ modulator exhibits certain nonlinearbehaviour. So its comprehensive analytical description has been both anabsorbing and confusing task. Hence simulation and measurement are thekey factor for a successful evaluation of the ΔΣ structure.This work is about high-quality decimation filters (digital sensors) forΔΣ modulator investigations. They are based on a two-phase(two-branch) parallel structure using recursive allpasses which areparticularly suitable for decimation by a factor of two. Moreover therepeated use of a basic decimation stage (BDS) makes this structurehighly modular and well fitted for silicon implementation. An importantBDS with only three coefficients (1/8, 9/16 and -1/16) has beenpresented in detail. Applied in the five stage decimator and compatiblewith CMOS technology, it achieves a 20-bit processing accuracy for thepassband of 20 kHz without the design complexity and cost penaltiesincurred in alternative approaches. The paper includes some designresults with performance evaluation under fixed point arithmetic. Thein-situ developed software tools are also described