A new technology for realizing high performance I2L and high speed ECL circuits on a same chip is described. The key to such a technology is graft base structure having respectively optimized impurity profiles for I2L gates and linear transistors. All of base regions (I2L; P+, P--, a linear transistor; P++, P-) are formed in different doping steps, followed by only one n+diffusion for I2L collector and the linear transistor's emitter. I2L P--intrinsic base region formed by high energy ion implantation has a smaller Gummel number and a deeper junction depth than in the linear transistor. I2L P+extrinsic base region is deeper in junction depth than linear P++base region. A high speed I2L gate with upward current gain of 30 and 7 ns minimum delay could be compatible with a linear transistor having downward current gain of 80, BVCEOof 18 V and 4 GHz maximum cut off frequency. Futhermore, an ECL divider has successfully operated at frequencies up to 1.4 GHz.
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机译：描述了一种在同一芯片上实现高性能I 2 L和高速ECL电路的新技术。这项技术的关键是针对I 2 L栅极和线性晶体管分别具有最佳杂质分布的接枝基础结构。所有基极区域（I 2 L; P + ，P -，线性晶体管; P ++ ，P -）在不同的掺杂步骤中形成，然后对I 2 L集电极和线性晶体管的发射极仅进行一次n + 扩散。与线性晶体管相比，通过高能离子注入形成的I 2 L P -本征基区具有更小的Gummel数和更深的结深度。 I 2 L P + 非本征基区的结深比线性P ++ 基区的深。向上电流增益为30 ns且最小延迟为7 ns的高速I 2 L栅极可以与向下电流增益为80，BV CEO 为18的线性晶体管兼容V和4 GHz最大截止频率。此外，ECL分频器已成功在高达1.4 GHz的频率下运行。
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