The versatility of verilog-A based models on commercial microwave simulators

摘要

Verilog-A Hardware Description Language (VHDL) is a behavioral description language for analog systems. It is derived from the IEEE 1364 Verilog HDL specification and it is intended to let designers of analog and integrated circuits to create and use modules described mathematically in terms of its terminals and external parameters applied to the module. This paper shows the simplicity and versatility technique of modeling active microwave devices using Verilog-A language. We have made several comparisons under two different commercial simulators: Agilent ADS and GENESYS.