Combined Inference and Satisfiability Based Methods for Complete Signal Restoration in Post-Silicon Validation

摘要

Forward inference and backward justification (FB) methods are commonly used for signal restoration in post-silicon validation and debug. We show that the FB method can miss a large number of restorable signal values. We propose a novel hybrid method, combining FB and satisfiability (SAT) checking based on time frames along with a signal prioritization heuristic, for efficient and accurate restoration of all signal values that can possibly be restored. Experimental results show that the proposed method can increase the signal restoration ratio by a factor of 18x. For large circuits where this method takes a long time and becomes impractical, we apply the time frames technique with SAT method employed locally in each frame to improve efficiency while compromising the restoration ratio. Using this method, experimental analysis shows up to 5x improvement in restoration ratio for large benchmarks.