Modeling Analysis of Redundancy Based Fault Tolerance for Permanent Faults in Chip Multiprocessor Cache

摘要

With increased number of cores in Multicore Chips, power consumption raises. Voltage scaling is applied largely but it causes cell failure in cache. For that, various techniques for fault tolerance in cache have been introduced. Among these techniques, the redundancy based technique is the most effective one but no analysis has yet been done to assess its performance. This work attempts to propose and evaluate the parameters like Expected Miss Ratio for Multicore (EMR_MC) and Expected Latency in Multicore (EL_MC), as the function of Probability of Cell Failure (P_fail) for redundancy based technique. It is found that both (EMR_MC) and (EL_MC) decrease with increased number of cores. The lower bound of P_fail i.e. 1e-4, up to which both (EMR_MC) and (EL_MC) in all architectures remain same. Above that both (EMR_MC) and (EL_MC) increases except for octacore. The (EMR_MC) for octacore starts increasing above P_fail of 5E-4 and converges with others for high P_fail like 0.005. On the other hand, the (EL_MC) for octacore is hardly affected up to high P_fail like 0.001 and above that though it increases but remains lower than others. Performance gain of up to 34.63% for (EMR_MC) and 45.67% for (EL_MC) is observed with increased number of cores.