Fault Tolerance in Network on Chip Using Bypass Path Establishing Packets

摘要

Network-On-Chip (NOC) plays a vital role in on-chip communication infrastructure for Massively Parallel System On Chip environment. Large size NOC networks are prone to fault(s) on links and routers. This paper presents a fault tolerant routing algorithm by setting up bypass path around faulty nodes. Experimental evaluation shows significant reduction in latency and better reliability over an existing technique and the baseline network.