ELURA: A Methodology for Post-Silicon Gate-Level Error Localization Using Regression Analysis

摘要

Limited observability of internal design states exacerbates the problem of error localization at post-silicon stage. With the assistance of system-level observed features, errors can be localized at higher design abstraction level during post-silicon validation. However, localizing error(s) at the gate-level becomes very difficult due to the tremendous design complexity of modern circuits. In this work, we propose a methodology for localizing error to a small portion of the gate-level design description based on a regression analysis of circuit responses to synthetically injected errors. The model learns the flip-flop states upon error introduction and given an actual erroneous netlist, provides ranking of infected flip-flops. The error localization analysis is done by testing with states of the flip-flops which are traced through trace buffer mechanism. On-chip trace buffers are capable of overcoming the obstacle of diminished observability, which can be further enhanced with the help of state restoration technique. We demonstrate that state restoration significantly improves error localization. Experimental results on benchmark circuits justify the efficacy of the proposed methodology on two gate-level error models which represent logical error manifestations.